1. Field of the Invention
The present invention relates to semiconductor memory devices and method of operating the same, and more particularly, relates to semiconductor memory devices adapted to burst transmission.
2. Description of the Related Art
The Static Random Access Memory (SRAM) is a typical semiconductor memory device used as a work memory for data processing. Using an SRAM as a working memory effectively achieves high speed data processing due to the enhanced operation speed.
The SRAM, however, often dissatisfies recent requirements of electronic devices due to the poor integration capability. Recent high-end electronic devices require a work memory having an increased capacity, and an SRAM may dissatisfy a required specification as a work memory. This necessitates an alternative semiconductor memory with an increased capacity, suitable as a work memory.
The pseudo SRAM is a semiconductor memory device satisfying such requirement. The pseudo SRAM designates a sort of dynamic random access memory (DRAM) with an external interface compatible with the SRAM. The pseudo SRAM, composed of DRAM memory cells suitable for high integration, can be used as a work memory with an increased capacity, providing the compatibility with the SRAM.
One drawback is that the pseudo SRAM suffers from the reduced access speed to the memory array, compared to the SRAM. This results from the fact that the access speed of DRAM cells within the pseudo SRAM is not as high as that of SRAM cells. Therefore, the improvement of the access speed is one of the most important issues for using a pseudo SRAM as a work memory.
Burst transmission is one known technique for improving the access speed of the pseudo SRAM. The burst transmission designates a technique for enhancing the transmission speed through successively transmitting read/write data associated with a series of addresses. The COSMORAM (Common Specifications for Mobile RAM) standard, which has been recently proposed for defining the functions of the pseudo SRAM interface, supports the burst transmission. Hereinafter, write operation based on burst transmission may be referred to as burst write operation, and read operation based on burst transmission may be referred to as burst read operation.
In order to improve the speed of burst write and read operations, pseudo SRAMs adapted to burst transmission often incorporate a set of registers for temporary storing write and read data; a register for storing write data may be referred to as a write register, and a register for storing read data may be referred to as a read register. The write operation of such designed pseudo SRAM involves sequentially storing write data associated with one burst cycle into the write register, and concurrently transferring the complete set of the write data from the write register to the memory array. The read operation, on the other hand, involves concurrently transferring a complete set of desired read data from the memory array to the read register, and sequentially outputting the read data from the read register. The concurrent data transfer between the memory array and the registers effectively reduces the number of accesses to the memory array, and therefore improves the access speed of the pseudo SRAM.
Partially transferring the write data stored in the write register to the memory array is considered as a preferred requirement for improving the flexibility of the burst write operation. Let us suppose a burst write operation sequence with the burst length being eight, which involves sequentially transferring eight data bits through each input/output pin during one burst cycle. In this burst write operation sequence, it would be advantageous for improving the data access flexibility of the memory array, if first to six data bits, for example, can be selectively transferred from the write register to the memory array.
Conventional pseudo SRAMs, however, are not adapted to selective data transfer of write data from the write register to the memory cells; pseudo SRAMs are conventionally designed to concurrently transfer the complete set of the write data. A special architecture is needed for satisfying such requirement.
As disclosed in Japanese Open Laid Patent Application No. P2003-7060A, synchronous DRAMs supporting burst transmission are designed to achieve selective data write into the memory array using the data mask signal (DQM signal).
The selective data write technique based on the data mask signal, however, is not applicable to the pseudo SRAM, because the standard SRAM interface is not adapted to the data mask signal.